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It appears that the #1 reason for the Parhelia's somewhat disappointing 3D-performance is the low clock speed of the board. The clock speed has even decreased from that of the alpha/beta boards! Why would matrox want to do this?
The usual explanation is that Matrox had to decrease the size of the heatsink to comply with the AGP physical specs. But surely they could have used an AGP-compliant heatsink that was a little less spartan? Look at the GF4 in its various forms! Did matrox even bother to use a thermal interface material between the chip and the heatsink?
I think the true reason for the low clock speeds might be a different one: power consumption. According to the AGP 2.0 specs, the maximum power consumption for the different voltage lines is:
3.3V * 6A = 19.8 W
5V * 2A = 10W
12V * 1A = 12W
(see ftp://download.intel.com/technology/...oads/agp20.pdf )
This gives a total of 41.8 Watts. In addition to this another 8 Amperes are available on the data lines, operating at 1.5 or 3.3V. However, the AGP2.0 document says that the actual currents on these lines will be smaller thatn 2 Amperes. So the current on these data lines can thus burn up 3 to 7 Watts. Everything adds up to around 45 Watts of power MAXIMUM!
The Parhelia in its current form uses 36 Watts running 3DMark 2001 SE Pro! (tested by the german tecchannel : http://www.tecchannel.de/hardware/907/39.html ). I imagine the Parhelia being quite busy running 3DMark, but its features aren't used to the fullest, so the 36 Watt figure is probably not even the maximum power the card can draw.
As far as I know the power consumption of a chip increases both when you increase the clock speed (linearly?) and the voltage (quadratically?). This leads me to think that Matrox had to decrease the clock speed and/or voltage of the Parhelia to remain within the AGP ELECTRICAL specs. They have to, because the one thing Matrox really cannot afford is risking its reputation as a producer of high quality, stable cards.
Suppose all this is true, how could Matrox get around this problem - they HAVE TO if they want to introduce a 256MB or MAX version. I see 3 possibilities:
1) Use an AGP PRO connector, with the risk of excluding a large customer base.
2) Equip the boards with an extra connector that sucks power directly form the power suppy. The extra connectors/circuitry would probably increase the board price even more.
3) Perform a die shrink, so the voltage can be decreased while the clock speed increases. This will take a while, though.
Does anyone else have any ideas on this?
The usual explanation is that Matrox had to decrease the size of the heatsink to comply with the AGP physical specs. But surely they could have used an AGP-compliant heatsink that was a little less spartan? Look at the GF4 in its various forms! Did matrox even bother to use a thermal interface material between the chip and the heatsink?
I think the true reason for the low clock speeds might be a different one: power consumption. According to the AGP 2.0 specs, the maximum power consumption for the different voltage lines is:
3.3V * 6A = 19.8 W
5V * 2A = 10W
12V * 1A = 12W
(see ftp://download.intel.com/technology/...oads/agp20.pdf )
This gives a total of 41.8 Watts. In addition to this another 8 Amperes are available on the data lines, operating at 1.5 or 3.3V. However, the AGP2.0 document says that the actual currents on these lines will be smaller thatn 2 Amperes. So the current on these data lines can thus burn up 3 to 7 Watts. Everything adds up to around 45 Watts of power MAXIMUM!
The Parhelia in its current form uses 36 Watts running 3DMark 2001 SE Pro! (tested by the german tecchannel : http://www.tecchannel.de/hardware/907/39.html ). I imagine the Parhelia being quite busy running 3DMark, but its features aren't used to the fullest, so the 36 Watt figure is probably not even the maximum power the card can draw.
As far as I know the power consumption of a chip increases both when you increase the clock speed (linearly?) and the voltage (quadratically?). This leads me to think that Matrox had to decrease the clock speed and/or voltage of the Parhelia to remain within the AGP ELECTRICAL specs. They have to, because the one thing Matrox really cannot afford is risking its reputation as a producer of high quality, stable cards.
Suppose all this is true, how could Matrox get around this problem - they HAVE TO if they want to introduce a 256MB or MAX version. I see 3 possibilities:
1) Use an AGP PRO connector, with the risk of excluding a large customer base.
2) Equip the boards with an extra connector that sucks power directly form the power suppy. The extra connectors/circuitry would probably increase the board price even more.
3) Perform a die shrink, so the voltage can be decreased while the clock speed increases. This will take a while, though.
Does anyone else have any ideas on this?
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