Help needed with g200clk

[franksch4]

When I run g200clk I get the following output:

-----8<----------------------------------------------------

G200CLK Matrox MGA-G200 Optimizer Version 0.21 Beta Release
1999(C) Copyright Matrox MGA Optimization Tools
All Rights Reserved. May 31, 1999.

Chipsets : Matrox MGA-G400 AGP
MGA Control Aperture : E4000000h
Mapped Linear Address : CAFAF000h

System PLL Parameters : M = 2, N = 27, P = 0, S = 3
System PLL Clock (Fo) : 252.00 MHz
Clock Dividers : GCLK = Fo/2.0 (126.00 MHz)
MCLK = Fo/2.0 (126.00 MHz)
WCLK = Fo/2.0 (126.00 MHz)

Hardware Plane Write Mask (SGRAM-only) : ENABLED
Enhanced PCI Master Read (MRL & MRM) : ENABLED

Memory refresh counter : 39 (2497 MCLK period)

-----8<----------------------------------------------------

I think that GCLK is the Graphics clock ie. core speed. MCLK is probably the memory clock. Don't know what the WCLK stands for.

I was under the impression that the memory clock divider for the G400 should be 1.5 instead of 2.0. Can somebody explain why g200clk shows that it is 2.0. Does g200clk just show it wrong? I did use powerstrip before. Could that be it? All help would be appriciated.

Frank Schoondermark

[Kruzin]

G200clk just reads that value wrong.
G4set will report it properly.